Experiments with Digital Logic

February 16, 2016 (with later updates)

This page documents some very basic digital logic devices I've built.

The Humble AND Gate

  1. Input A to the AND gate, a push-button.
  2. Input B to the AND gate.
  3. The 74HC08, which contains four AND gates.
  4. The output of the AND gate; this LED lights up when both buttons are pressed.

Full Adder

This is a schematic of a full adder, copied shamelessly from the internet. (The gate marked with an asterisk can be either an OR or an XOR gate, with no effect on behavior.)

My implementation uses three chips, but a full adder requires only five of the 12 gates in those chips.

  1. (DIP switches) Inputs to the full adder:
    1. Input value A
    2. Input value B
    3. Carry-in
  2. Output S, the sum of the three inputs.
  3. Output C, the carry bit; HIGH if at least two of the inputs are HIGH.
  4. (74HC86) Two XOR gates are used in the adder.
  5. (74HC08) Two AND gates are used in the adder.
  6. (74HC32) One OR gate is used in the adder.

4-bit Counter

This is just a simple circuit to exercise the functionality of a 74HC161 4-bit counter. A major flaw of this circuit is that the "increment" button, A, is not de-bounced, so the counter will often increment more than once when the button is pressed. I had no capacitors when I assembled this circuit, so I couldn't fix this.

  1. Increment the counter.
  2. An LED attached to the overflow pin of the counter; it turns on when the counter is at its max value of 1111.
  3. (74HC161) The counter.
  4. Reset the counter to zero.
  5. An LED bar showing the current value of the counter.

Chained Counters

February 19, 2016

This circuit demonstrates how 74HC161 counters can be chained to create larger counters. In this case, two 4-bit counters are combined to create an 8-bit counter.

Notably, the best way to do this is to connect the "carry out" pin on the first counter to the "carry in" pin on the second counter -- not to its clock pin! Sending the "carry out" to the clock pin will work, but it makes it difficult to also use the load functionality, which is synchronous. (In the datasheet, the "carry in" pin is called CET -- "count enable trickle" -- which does not make its significance clear.)

  1. Reset both counters to zero.
  2. Increment the combined counter.
  3. The counter chips. (74HC161) The counter on the right stores the low 4 bits, and the one on the left stores the high 4 bits.
  4. This yellow-orange wire transmits the carry-out signal from the low-order counter to the second counter. This is where the chaining happens.
  5. An LED bar showing the current value of the chained counter. Only the middle 8 LEDs are used, and the leftmost of those LEDs is the most-significant-bit of the counter value. The counter's value is currently 0x2A.

The Full Adder Chip

February 23, 2016

This circuit demonstrates the 74HC283 4-bit Full Adder. This chip adds together two 4-bit binary values and produces a 5-bit sum. (The fifth bit is the carry-out bit, which could be chained to another adder.)

  1. The input: One four-bit value is entered with the left four switches, and the other is loaded with the right switches.
  2. The full adder. (74HC283)
  3. The output LEDs. This circuit is adding 0xA + 0x9, producing 0x13.

A BCD Adder

February 23, 2016

This circuit adds together two 4-bit BCD digits, producing a BCD sum and a carry bit. It works as follows:

The input values must be valid BCD digits between zero and nine. Add the input values together with ordinary two's-complement addition. This intermediate sum will be between 0 and 18.

In this photo, 0 + 7 = 7 is calculated. Since the result is not greater than nine, it behaves just like binary addition and there is no overflow.

  1. This is the first adder, which computes the intermediate sum.
  2. These AND and OR gates detect when the intermediate sum is greater than nine. When this is true, the BCD carry-out bit is set and six will be added to the intermediate sum.
  3. The second adder adds six to the intermediate sum if BCD overflow was detected in the previous step.

In this photo, 0 + 15 = 15 is calculated. (This isn't valid input to a BCD adder, but the result in this case is no different than adding 8 + 7.) Since the sum is greater than 9, the BCD overflow detector kicks in, enabling carry-out and adjusting the sum to properly wrap around from nine to zero.